SSM9926A comman drain dual n-channel enhancement mode mosfet product summary p r o d u c t s u m m a r y v ds (v) i d (a) 20v 6a r ds(on) (m ? ) max 30 @v gs = 4.0v 40 @v gs = 2.5v south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor, october 2006 (rev 2.0) 1 absolute maximum ratings (t a b s o l u t e m a x i m u m r a t i n g s ( t a = 25 c unless otherwise noted) = 2 5 c u n l e s s o t h e r w i s e n o t e d ) thermal characteristics t h e r m a l c h a r a c t e r i s t i c s parameter symbol limit unit o drain-source voltage gate-source voltage drain current-continuous @ t c = 25 c -pulsed drain-source diode forward current maximum power dissipation operating junction and storage temperature range thermal resistance, junction-to-ambient o a a a b v ds v gs i d i dm i s p d t j , t stg r ja 20 v v a a a c/w w c o o ? 10 6 35 1.7 2 -55 to 150 62.5 sop-8 d 1 (7, 8) g 1 (2) s 1 (1) 1 2 3 4 5 6 7 8 g 2 (4) s 2 (3) d 2 (5, 6) features ?5p super high dense cell design for low r ds(on) . ?5p rugged and reliable. ?5p sop-8 package. ?5p pb free.
SSM9926A 2 n-channel electrical characteristics (t n - c h a n n e l e l e c t r i c a l c h a r a c t e r i s t i c s ( t a = 25 c unless otherwise noted) = 2 5 c u n l e s s o t h e r w i s e n o t e d ) o unit symbol parameter condition min typ max c zero gate voltage drain current drain-source breakdown voltage gate-body leakage gate threshold voltage drain-source on-state resistance bv dss i dss i gss v gs(th) r ds(on) v gs =0v, i d =250 ? a v ds =16v, v gs =0v v gs = ? 10v, v ds =0v v ds =v gs, i d =250 ? a v gs =4.0v, i d =6a v gs =2.5v, i d =3a m ? v v ? a na 20 1 ? 100 1.5 30 40 0.5 on-state drain current forward transconductance turn-on delay time rise time turn-off delay time fall time i d(on) g fs t d(on) t r t d(off) t f v ds =5v, v gs =4v v ds =5v, i d =4a v dd =10v, v gen =4.5v, r l =10 ? 30 12 ns p f s a input capacitance output capacitance reverse transfer capacitance c iss c oss c rss v ds =8v v gs =0v f=1.0mhz total gate charge q g i d =1a, r gen =10 ? , diode forward voltage v sd v gs =0v, i d =1a v gate-source charge gate-drain charge q gs q gd i d =4a, v gs =4.5v nc 0.8 v ds =10v, notes j a. surface mounted on fr4 board, t <10 sec. b. pulse test j pulse width < 300 ? s, duty cycle < 2%. c. guaranteed by design, not subject to production testing. - -- 5 44 20 18 810 155 125 11 0.8 3 1.2 25 35 2.5
SSM9926A 3 v ds , drain-to-source voltage (v) i d , drain current (a) figure 1. output characteristics 0 2 4 6 8 10 12 20 16 12 8 4 0 v gs , gate-to-source voltage (v) i d , drain current (a) figure 2. thansfer characteristics 0 0.3 0.6 0.9 1.2 1.5 1.8 25 20 15 10 5 0 r ds(on), on-resistance normalized ( ? ) figure 4. on-resistance variation with temperature v gs = 4v t j , junction tempertature ( c) o i d = 4a v ds , drain-to-source voltage (v) c, capacitance (pf) figure 3. capacitance 0 2 4 6 8 10 12 vth, normalized gate-source threshold voltage tj , junction temperature ( c) figure 5. gate threshold variation with temperature o v ds = v gs i d = 250 ? a 1.2 1.1 1.0 0.9 0.8 0.7 0.6 bv dss , normalized drain-source breakdown voltag e figure 6. breakdown voltage variation with temperature tj , junction temperature ( c) o 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d = 250 ? a v gs = 2v v gs = 10, 9, 8, 7, 6, 5, 4, 3v -50 -25 0 25 50 75 100 125 -55 c o 25 c o tj = 125 c o 0 300 600 900 1200 1500 coss ciss crss 0 0.2 0.6 1.0 1.4 1.8 2.2 1.3 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
SSM9926A 4 i ds , drain-source current (a) g fs, transconductance (s) 0 4 8 12 16 20 figure 7. transconductance variation with drain current i s , source-drain current (a) 20.0 v sd , body diode forward voltage (v) figure 8. body diode forward voltage variation with source current 0.4 0.6 0.8 1.0 1.2 1.4 v gs , gate to source voltage (v) figure 9. gate charge qg , total gate charge (nc) 0 2 4 6 8 10 12 14 16 5 4 3 2 1 0 v ds = 10v i d = 4a i d , drain current (a) 0.01 v sd , drain-to-source voltage (v) figure 10. maximum safe operating area 0.1 1 10 30 50 50 10 1 0.1 v gs = 10v single pulse t a = 25 c o 30 10 5 0 10.0 1.0 v ds = 5v 15 20 25 r ds(on) limit dc 1s 100ms 10ms
SSM9926A 5 figure 11. switching test circuit v gs r gen v out v dd v in d r l g s figure 12. switching waveforms inverted pulse width t r t d(on) v out v in t on t off t d(off) t f 10% 50% 50% 90% 10% 90% 10% 90% figure 13. normalized thermal transient impedance curve t1 t2 p dm 1. r ja(t) = r(t)*r ja 2. r ja = see datasheet 3. t jm - t a = p dm *r ja(t) 4. duty cycle, d = t1/t2 1 10 -4 10 -3 10 -2 10 -1 10 -5 0.01 1 0.1 10 r (t), normalized effective transient thermal impedance duty cycle = 0.5 square wave pulse duration (sec) 10 10 2 10 3 0.2 0.1 0.0.5 0.02 0.01 single pulse
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